State-of-the-art IP cores require adequate verification methods
Growing complexity of IP cores means much more testing necessary to guarantee the excellence of the
product. Evatronix introduced the 0-in® formal verification tools into its design flow for both
acceleration and highest precision of the verification process. The diagram below pictures the
current IP design and verification flow, while this joint publication of Evatronix and Mentor
Graphics explains all whys and wherefores of introducing formal verification.
