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SPRINT
Goal of the SPRINT project is to define standards for efficient reuse and integration of IP modules.The project
will provide an SoC design methodology and standards based on TLM and SPIRIT programs, enabling integration
of interoperable and reusable IPs. Such an approach will improve design productivity and quality of an SoC design.
Project started in 2006 with a timeframe of 3 years.
The works are divided into five technical, one management and one dissemination workpackages.
Technical workpackage is divided into PCD designs, high-level modelling, communication interfaces, debug tools
and verification. An expected result of the project is 10 times faster integration and 500 times greater
simulation speed (both values presented in comparison to RTL).
European semiconductor companies, IP providers, EVA vendors, universities and research institutes participate in the project.
The list includes NXP, ST Microelectronics, Infineon, Syosil, Magillem Design Services,
University of Paderborn, KeesDA, TIMA, KTH, ECSI, ARM, Lauterbach, and Coware.
Evatronix acts as IP provider in the project .
Its main role is to deliver IP modules for the Proof of Concept Designs developed in the SPRINT project.
Evatronix develops both state-of-the-art and project-defined views of the delivered IP.
Evatronix also participated in the definition of technical requirements for the SPRINT standards
and takes part in development of standalone testbenches and reusable built-in assertions for IP integration validation.
Thanks to participation in the SPRINT project Evatronix is be able to meet market expectations and
ensure seamless integration of its IP cores into customers' designs.
SPRINT project website
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MAPPER
The MAPPER project's goal is integrate the heterogeneous processes, products, systems and services of
manufacturing enterprises, enabling sustainable business ecosystems. This can be done by integration of enterprise
modelling, participative methodologies, collaborative customisation, and secure, distributed tool invocation
into an open, visual, holistic, and reconfigurable collaboration platform.
By using MAPPER results, enterprises can transform into dynamically networked organisations.
Integrative, holistic views of the joint enterprise will lower today's friction and process
losses, resulting in more effective operations, innovative designs, and increased business
opportunities. This approach aims at extension of Europe's competitive advantage, such as agility,
skills and competence of the workforce.
Evatronix is one of main MAPPER participants. Its close cooperation with Advico, German microelectronics company,
results in application of MAPPER tools and methologies to electronic designs.
MAPPER project website
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PRO_NMS
The project PRO_NMS addresses research organisations, SMEs, IT companies mainly from New Member States (NMS)
- Poland, Slovakia, Latvia, Lithuania, Estonia, Hungary and one NIS country - Ukraine- to enlarge the
participation in Framework Programmes. These countries will be accompanied by partners from Austria and Germany.
The consortium will reach the potential proposers to 5th IST Call as well as to future IST actions (FP 7th)
from key IST fields - Micro/nano based sub-systems, Embedded Systems and ICT for Networked Businesses.
The PRO_NMS consortium will in three of proposed Strategic Objectives (IST research and technology areas
common to all partners) facilitate the participation of organisations from the New Member States (NMS) in
the activities of IST establish the partnership of research organisations from the NMS with organisations
from the other MS.
PRO-NMS project website
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