In order to ensure high quality of our IP cores a Quality Management System was defined and implemented. In March 2003 it was successfully audited for its compliance to ISO 9001:2000 standard.

We apply a rigorous development methodology in order to ensure the compliance of our IP cores to reference architectures. Equivalent testbench environments are developed for hardware modeler and its accompanying simulator as well as for the VHDL simulator. This enables us to compare simulation results with a reference chip behaviour.

Design rules for HDL coding are checked with LEDA from Synopsys, Inc. Test suite quality is measured with the VN-Cover, the leading code coverage tool from TransEDA. All cores are prototyped in FPGAs, and then verified through extensive software testbenches and hardware environments. For obsolete parts replacement products, the prototype is first tested with the hardware modeler and its behaviour is compared towards that of a reference chip. Application environment is then developed and the core prototype is tested in it.

Reuse Methodology Manual (by Synopsys and Mentor Graphics) and VSI Alliance Specifications guidelines are followed throughout the development, verification and productization process to ensure high QIP Metric rating for our cores.

For specific system bus interfaces (AMBA® AHB) Mentor Graphics 0-in formal verification tools have been introduced to ensure the components' compliance within the System-on-Chip. Read more here.

Many of our cores have been introduced by our strategic partner, CAST, Inc., into the third party IP programs run by Altera (AMPP) and Xilinx (Xilinx Alliance Program) as well as Actel (CompanionCore) and Lattice (ispLeverCore).