Evatronix Demonstrates Transactional Model of USBHS-OTG Controller

ECSI to host SPRINT Project Participants at its Booth (M12) at DATE’2007

Gliwice & Bielsko-Biala, Poland, April 16, 2007 - The silicon Intellectual Property (IP) provider, Evatronix SA, today announces the USBHS-OTG-TLM, a transaction-level model USB OTG controller corresponding to USBHS-OTG-MPD RTL IP core.

Transaction level modelling is gaining interest because of its flexibility in handling different abstraction levels and separating on chip communication issues from the functionality of the submodules, created in hardware or in software. Supported with a new breed of hardware description languages (like SystemC and to some extent System Verilog) it has become an important technique that enables shifting the design activities above the RTL abstraction level. SystemC TLM standard defines basic mechanisms for parallel systems modelling, but many aspects have been left and may cause incompatibilities with the TLM models from different sources. This hampers the reusing of such models. One of the main goals of the SPRINT Project is standardization of technologies related to SoC development and SystemC TLM models. The expected result of the SPRINT project is to provide a 500x increase in simulation speed over RTL and a 10x SoC integration effort reduction.

Evatronix joins the Project as an IP Vendor. The company delivers IP modules for the Proof of Concept Designs and develops all required views of the delivered IP - both state-of-the-art and new ones defined in the project. In this way Evatronix customers will be able to seamlessly integrate Evatronix IP cores into their SoC designs.

“TLM has become the right Level of Abstraction and creates a reliable base for an effective concurrent design of software / hardware components of System-On-Chips and wide IP reuse, thus becoming a common practice in SoC design which provides substantial productivity” – said Wojciech Sakowski, Evatronix President. ”Evatronix is committed to keeping up with the evolving requirements of major SoC integrators”, he added.

Evatronix will present the TLM model at the ECSI booth at the DATE 2007 event, which takes place in Nice (France) from April 16th to 20th.

“The substantial increase of the productivity in SoC integration is now becoming possible thanks to two major factors that are enabled by modelling at transactional level: the verification performance increase and the concurrency in the development process of application software and underlying HW platform. This will boost the provision of IP models at the TLM that are ready to be integrated and verified in the complete SoC. Evatronix, as one of very few companies, develops the first TLM models of their IPs in the context of the SPRINT project presented at the ECSI booth at the DATE Exhibition.” - said Adam Morawiec, director of the European Electronic Chips & Systems design Initiative (ECSI).

Along with having a booth ECSI will run a panel, which will present the industrial positions on the state-of-the-art and prioritization of future tendencies in SoC design in multi-language and multi-abstraction-level design environment. The focus will be on the particular requirements from specific application areas. The context of standardization progress within OSCI, SPIRIT, Accellera, OCP-IP and IEEE/DASC as well as emerging contributions from large European R&D projects like SPRINT will be discussed. It will also address the priority of the evolution of languages, modelling techniques and associated standards and show probable evolution trends.

About the USBHS-OTG-MPD IP core and its TLM Model

The USBHS-OTG-TLM is a transaction-level model of Evatronix synthesizable USBHS-OTG-MPD serial bus interface controller core. This core complies to USB 2.0 with OTG Supplement to USB 2.0 specification and was certified at the USB-IF Compliance Workshop in February, 2006. USBHS-OTG-TLM functionality models subset of USBHS-OTG-MPD core including advanced features such as latency buffers and USB protocol-aware multichannel DMA. The organization of the buffers, using system memory as endpoint storage location, significantly reduces the size of expensive on-chip memory and allows users to optimize memory resources management according to the needs of the system. More information about USB-OTG-MPD can be found at www.evatronix.pl.

The USBHS-OTG-TLM model was developed as a transactional PV+T (Programmer's View with Timing) model using C++ language and SystemC library. It makes initial testing of the USB related software very convenient thanks to model debugging features, in particular the possibility of checking the state of each submodule. Achievable simulation speed of the model makes such an approach a viable alternative to testing the software with the hardware prototype, which enables parallel development of software and hardware.

USBHS-OTG-MPD Software Stack, written in portable ANSI-C, can be easily integrated with USBHS-OTG-TLM. It is done by a few modifications in the hardware-dependent layer, such as wrapper class development, that behaves exactly like pointer but calls registered functions for each access attempt.

For more information about USBHS-OTG-TLM please contact: ipcenter@evatronix.pl.

About SPRINT

The SPRINT (Open SoC Design Platform for Reuse and Integration of IPs) Project is partly funded under the European Union's IST Sixth Framework Program and partly by the project members. The alliance was started in February for an initial period of 30 months till mid-2008 to research and promote open interface and modeling standards for IP integration. Project members include chipmakers NXP Semiconductors, STMicroelectronics and Infineon Technologies; IP vendors ARM, Evatronix SA, and Syosil; EDA vendors Magillem, Spiratech, Lauterbach and KeesDA; research groups at Paderborn University, TIMA and the Royal Institute of Technology (KTH); and the ECSI association for training and dissemination. More information on the SPRINT Project can be found at www.sprint-project.net

About Evatronix

Evatronix SA, headquartered in Bielsko-Biala, Poland, develops electronic virtual components (IP cores) and provides design services in the field of SoC engineering to electronics companies, globally. The company’s main design office is located in Gliwice (Poland) that guarantees easy access to the talent pool of graduates from the Silesian University of Technology. Evatronix IP cores are available worldwide through the sales channels of its strategic distribution partner CAST, Inc. (New Jersey, USA). In Switzerland and the European Union countries (excluding UK) Evatronix also operates a direct sales channel. For more company information and product portfolio, please visit www.evatronix.pl.