- Supports standard and extended spare area devices from Samsung, Micron, STMicroelectronics, Toshiba and others
- Internal OCP socket for straightforward implementation of the core into a variety of system interfaces
- AMBA® interface that supports AHB 2.0 specification
- ONFi standard compatible
- Error Correction Code (ECC)calculation and data correction through Hamming and BCH 4/8/16 algorithms
- Memory type independence for each channel
- Automatic Write/Read Page with data correction
- Power Save Mode
- Boot sequence solution
- Support for both SLC and MLC memory types
- Seamless SoC integration with a built-in OCP socket
- The BCH algorithm allows up to 16-bit error correction
- Cut application-obsolete functional blocks for significant silicon savings with the user-friendly IP configuration script
- 32-bit NAND Flash IO bus increases the data transfer bandwidth up to 4 times
- Available NAND Flash low-level software driver allows to develop application software without detailed NAND Flash controller knowledge
- Optional software driver for third party Flash File Systems and Flash Translation Layer allows building complete solution for Windows CE or other RTOS
- Support for ONFi standard speeds time-to-market for products basing on NAND Flash memory
- Ability for software change of the page size between 2 and 4 kB (only if 4 kB page size is selected in the hardware configuration script)
- Mass Storage - USB flash drives, digital cameras, digital voice recorders,
- Embedded Storage — cellular phones, network routers, point of sale systems.
Related productsNANDFLASH-CTRL DRIVER - it is low-level software driver that represents a first abstraction layer of the NANDFLASH-CTRL controller to relieve the higher level application layer from the hardware management.
NANDFLASH-CTRL WinCE Software Driver – a wrapper between the Evatronix NANDFLASH-CTRL Driver and the Windows CE interface.
NANDFLASH-CTRL CMX Software Driver - a wrapper between the Evatronix NANDFLASH-CTRL Driver and the CMX File System interface.
CMX-FFS-FAT (from CMX Systems) - a full-featured file system for embedded systems developers who wish to add devices to their products that require FAT12/16/32 compliant media to be attached to them. CMX-FFS-FAT features includes Long filenames, Multiple Volumes, Media Error handling, Mix of Media, Check Disk and drivers for Compact Flash (True IDE and Memory I/O), MMC/SD (SPI S/W or H/W) and RAM.
CMX-FFS-FAT-FTL (from CMX Systems) - a Flash Translation Layer that provides a reliable interface for NAND flash or DataFlash. This Translation Layer allows the file system to manage flash and provides a logical sector interface to the embedded host. The Flash Translation Layer can support up to 4 Terabytes for each array, provides 528, 2112 and 4224 byte pages and supports all standard NAND devices.
NAND Flash Memory Controller
OverviewThe NANDFLASH-CTRL IP core for high-capacity Multi-Level Cell (MLC) and traditional Single-Level Cell (SLC) NAND Flash memories provides System-on-Chip developers with a comprehensive way to minimize time-consuming hardware and software development as well as leverage emerging embedded application technologies.
To facilitate integration of the IP core into a system bus, the NANDFLASH-CTRL implements an OCP socket and is delivered with a wrapper for AMBA® AHB interface.
The NANDFLASH-CTRL features one of the most advanced error correction mechanisms, the BCH Error Correction Code that allows to correct up to 16 bits of errors.
Functional DescriptionThe NANDFLASH-CTRL core is partitioned into modules and comes with external elements as shown in the block diagram and described below.
A BIU component opens a window in the address space where the BUFFER and all SFRs are visible, providing access to these elements.
The main subcomponent responsible for handling NAND Flash memory devices. It comprises a set of SFRs that define the parameters of transfer to/from Flash memory. The FSM monitors an flcomm SFR register (instruction register) and makes an appropriate action defined by any instruction appearing as a new value in flcomm. The FSM sends information to BIU that it is busy and can’t accept a new instruction during instruction execution, and when finished sets a status flag indicating whether the instruction was executed correctly or not.
It speeds up data transfer between a device on the AHB bus and NAND Flash memory as well as decreases AHB bus burden.
Clocks signals hclk and fclk. The hclk signal is a system clock and it works all the time. The fclk signal is a controller clock turned off in Power Save Mode.
An internal memory used by the FSM during the automatic Page Read/Write process.
The Arbiter component is responsible for granting access to buffer for others controller subcomponents.
The ECC component is responsible for the detection and correction of the errors in page data area, which can occur during work with the NAND Flash memories. Error handling is realized automatically when transfer is done with the used buffer.
AHB WRAPPER SL
This block connects BIU to the external AHB bus.The wrapper translates OCP interface transactions to the AHB bus transactions.
AHB WRAPPER MS
This block fulfills the same function as AHB WRAPPER SL block. In this case block realizes functionality of the AHB Master bus.
Example ApplicationA typical application for the core is in an external mass storage device such as a USB pen drive, as shown in the block diagram.
The chip-level NANDFLASH-CTRL core is implemented with an internal buffer and tri-state buffers. Data is read/written from/to the NAND Flash memory through a USB controller with an AHB interface. The C68000 Microprocessor manages data flow, sets parameters of data transmission for NANDFLASH-CTRL, controls USB work, and handles all aspects connected with a File System implemented in this storage device.