Evatronix provides its customers with the soft & firm IP cores (virtual components) to enable them cut time-to-market for their system-on-chip designs. Our cores are developed according to the reusability rules and guidelines published by Michael Keating (Synopsys, Inc.) and Pierre Bricaud (Mentor Graphics Corp.) in their Reuse Methodology Manual. Its quality is measured by OpenMORE questionnaire and is ABOVE 90% of this measure for all cores.

Deliverables for the cores include:

• VHDL or Verilog RTL source files (source code licence only)
  or
• post-synthesis netlist targeted at FPGA technology of choice (optional for source code delivery)
• an example of synthesizable top level of the design that instantiates technology dependent components such as tri-state buffers and memories (if needed)
• complete VHDL or Verilog testbench
• (contains the example instantiation of the core and set of test bench elements - stimulators, comparators, monitors, etc.)
• Test Suite, a set of test cases that run within the test environment covers every core\'s functionality listed in Test Plan
• Compiled simulation model (optional deliverable for netlist versions)
• User documentation:
  • Design Specification
  • Integration Manual
  • Verification Specification and Test Plan
• A set of simulation support scripts and macros
  Supported simulators:
  • ActiveHDL by Aldec Inc.
  • ModelSim by Mentor Graphics
  • NCSim by Cadence
  (for the netlist version list of simulators may be different)
  Synopsys Design Compiler support for (not included in the FPGA netlist delivery):
  • Time optimized synthesis
  • Area optimized synthesis
  • Boundary scan insertion
• Place & Route scripts and constraint files for Altera Xilinx FPGA families

We offer also firm versions of the cores for Altera and Xilinx technologies. A netlist description for Altera or Xilinx devices instead of the RTL source code is then delivered to the customer (at lower cost). Some of our cores are available through Altera AMPP and Xilinx AllianceCORE programs.